Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulation gate type semiconductor device for a power device. In the trench gate type semiconductor device, generally, high breakdown voltage and low on resistance are in the relationship of trade-off.
The present applicant has proposed an insulation gate type semiconductor device 900 as depicted in FIG. 14 as a trench gate type semiconductor device that solved the problem (Japanese Patent Application No. 2003-349806 (Japanese Published Unexamined Patent Application No. 2005-116822)). The insulation gate type semiconductor device 900 is provided with N+ source regions 31, an N+ drain region 11, a P− body region 41, and an N− drift region 12. Also, gate trenches 21 that passes through the N+ source region 31 and P− body region 41 is formed by trenching a part of the upper surface of a semiconductor substrate. Further, a deposited insulating layer 23 is formed on the bottom of the gate trench 21 by deposition of an insulator. Also, a gate electrode 22 is formed on the deposited insulating layer 23. And, the gate electrode 22 is faced to the N+ source region 31 and P− body region 41 via a gate insulating film 24 formed on the wall surface of the gate trench 21. Further, P floating regions 51 is formed in the N− drift region 12. And, the lower end of the gate trench 21 is positioned in the P floating region 51.
The insulation gate type semiconductor device 900 is provided with the P floating region 51 in the N− drift region 12 and has the following characteristics in comparison with the insulation gate type semiconductor device not having the same. That is, when the gate voltage is switched off, a depletion layer is formed from the PN junction point with the P− body region 41 in the N− drift region 12 by voltage between the drain and the source (hereinafter called “between D and S”). And, the peak of electric field intensity is brought about in the vicinity of the PN junction point. As the tip end of the depletion layer reaches the P floating region 51, the P floating region becomes in a punched-through state to cause the potential thereof to be fixed. Further, where the application voltage between D and S is high, a depletion layer is formed from the lower end part of the P floating region 51. And, the peak of electric field intensity is brought about in the vicinity of the lower end part of the P floating region 51 in addition to the PN junction points with the P− body region 41. That is, the peak of the electric field can be formed at two points, wherein the maximum peak value is lowered to achieve high breakdown voltage. Also, since high breakdown voltage is secured, the impurity density of the N− drift region 12 is raised to achieve low on resistance.
In addition, the insulation gate type semiconductor device 900 is provided, at the terminal area thereof, with terminal trenches 62, which is composed so as to pass through the P− body region 41, and a P floating region 53, which is formed by implanting impurities through the bottom part of the terminal trench 62, as shown in FIG. 15. Therefore, production thereof can be simplified, and the terminal area can be made compact.
In detail, since, in the insulation gate type semiconductor device 900, the structure of the terminal area is almost the same as a cell area structure, a number of processes can be commonly used in both the areas. That is, since it is possible to simultaneously carry out processing in both the areas, the production can be simplified.
Also, as in the prior arts, if it is in the manner that the breakdown voltage of the terminal area is retained by guard rings, it is necessary to secure an area equivalent to or greater than the depletion layer spread toward the terminal area in the N− drift region 12 as an area of the guard ring layer. For this reason, the area of the guard ring layer hinders compaction of the entirety of a semiconductor device. On the other hand, in the insulation gate type semiconductor device 900, spread of the depletion layer spread in the N− drift region 12 in the plate surface direction (that is, in the N− lateral direction in FIG. 15) is interrupted by the terminal trench 62, and a lowering in the breakdown voltage in the terminal area by the P− floating region 53 as in the cell area is deterred. That is, high breakdown voltage can be achieved without spreading the terminal area.
In addition thereto, as a semiconductor device having a floating region in the drift region, in which spread of the terminal area is suppressed, for example, a semiconductor device disclosed by Patent Document 1 exists.
[Patent Document 1] Japanese Published Unexamined Patent Application No. 2001-15744
However, there are the following problems in the insulation gate type semiconductor device 900 described above. That is, although the breakdown voltage structure in the cell area and the breakdown voltage structure of the terminal area have roughly the same structure, they may differ from each other depending on whether or not a gate electrode is internally incorporated in the trench. For this reason, a difference arises in the spread of the depletion layer spread along the trench. Therefore, there may be a case where the breakdown voltage of the terminal area differs from the design breakdown voltage in the cell area. As a result, there may be a case where the breakdown voltage is lowered. For example, in the vicinity of the terminal trench 62 in which no gate electrode is internally incorporated, it is difficult for the depletion layer to spread in comparison with the vicinity of the gate trench 21. Accordingly, there is a fear that the depletion layer formed of PN junction points with the P− body region 41 is not connected to the depletion layer formed of the P floating region 53. Also, similarly, there is a fear that the depletion layer formed of the P floating region 51 is not connected to the depletion layer formed of the P floating region 53.
In addition, in regard to the semiconductor device disclosed by Patent Document 1, the breakdown voltage structure in the cell area differs from the breakdown voltage structure in the terminal area. That is, the depletion layers are different from each other in regard to the spread, wherein there may be cases where predetermined breakdown voltage cannot be obtained.
The present invention was developed to solve the problems that exist in the prior art semiconductor device described above. That is, it is therefore an object of the invention to provide an insulation gate type semiconductor device and a method for producing the insulation gate type semiconductor device, with which both high breakdown voltage and compactness can be secured.